The present invention relates to the execution of macro instructions by a central processing unit utilizing sequences of microcode instructions.
In a typical modern computer, a program is executed by fetching an instruction from memory and placing it in an instruction register. The instruction is then decoded to point to a starting address or series of addresses in a microcode memory. The microcode memory provides the operations which make up the instruction. The various operations from the microcode memory are sequentially placed into a micro instruction register where they are decoded to produce control signals for executing the operations. These control signals may enable an access of memory, the placement of operands into an arithmetic logic unit, the combination of operands in an arithmetic logic unit, etc. After all the microcode operations for a particular macro-instruction have been executed, a new macro-instruction is fetched from memory and the process is repeated.
Once the macro-instruction has been decoded, there is typically no interaction between the micro coded operations and the macro-instruction except for instances in which the macro-instruction includes a data operand or a register specifier for a data operand.
In efforts to speed computer operation, attempts have been made to shorten the number of clock cycles required for the macro instructions. One method of doing this involves performing redundant microcode operations and storing the results of these operations in separate registers where necessary. The next macro-instruction can then be decoded to determine whether it requires these operations. If it does, the precomputed results can be used. If not, the result of the redundant operation is thrown out. Unfortunately, this method requires a significant amount of additional hardware and often results in wasted operations. This type of scheme is employed in the TXP and VLX processors manufactured by Tandem Computers, Inc.
Another method involves processing multiple microcode instructions at one time to do some operations not requiring the ALU in parallel with ALU operations. The advantages of increased speed and simplified control logic are balanced by the disadvantage of requiring more hardware and making microcode branches slower.
Another method involves simply hardwiring certain macro-instruction operations so that microcode does not have to be accessed at all for such operations. The obvious disadvantage of this method is that the hardwired circuit becomes dedicated to that function and can't be used for other purposes.
U.S. Pat. No. 4,312,034 describes yet another method for reducing the amount of time required to execute a macro-instruction. Referring to FIG. 15 of that patent, a macro-instruction register (IRD) and a ROM output register (microcode) are factored into a ROM address whose outputs control an ALU and condition codes. Thus, the macro-instruction itself is used to control the ALU and condition codes instead of relying on the microcode instructions entirely. Thus, for example, to do an add or subtract operation the microcode would simply do the same fetch operation with the controller looking directly to the macro-instruction to determine whether to add or subtract.